1. Field of the Invention
The present invention relates to field programmable devices, and more specifically to a method and apparatus for implementing complex clock designs in such devices.
2. Related Art
Field programmable devices (FPD) generally refer to pre-fabricated logic circuits which can be programmed to implement a circuit logic. A typical FPD contains many cells, which can individually be programmed to one of several pre-specified logic blocks (e.g., a logic gate or a sequential element) and can be interconnected in a desired fashion to implement a desired circuit logic. Examples of FPDs include FPGAs (field programmable gate arrays) and programmable logic devices (PLDs) as is well known in the relevant arts.
FPDs find application in several areas. For example, an entire circuit logic can be implemented using FPDs quickly without having to engage in expensive and time-consuming tasks such as implementing masks for fabrication of individual integrated circuits. As another example, FPDs are used for prototyping circuits to ensure at least some aspects of the proposed circuit logic can be verified.
FPDs generally need to support implementation of complex clocks since such clocks would be required in at least some circuit logics. For example, some or all of derived clocks, divided clocks, gated clocks, independently generated clocks, etc., may be generated and/or used in different parts of a circuit logic.
One typical requirement in having such complex clocks is to ensure that the time delay (‘skew’) between two clock signals is within a pre-specified value. If the skew is higher than the pre-specified value, various anomalies such as unpredictable results may be caused, as is well known in the relevant arts.
In one prior approach, an FPD (while being manufactured) may be designed to provide a small number of clock buffers which provided limited skew, thereby addressing the problem noted above. However, one problem with such an approach is that a circuit logic may contain several more (number of) clock signals, and accordingly the corresponding solutions may be inadequate.
In view of problems such as above, a designer may spend a substantial amount of time addressing the clock related problems, and accordingly such solutions are not acceptable at least in some environments (e.g., when rapid prototyping is desirable). What is therefore needed is a method and apparatus to implement complex clock designs in FPDs.
In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number.